NAME
apic,
ioapic,
lapic
—
Intel APIC Architecture
SYNOPSIS
ioapic* at mainbus*
DESCRIPTION
The
apic subsystem provides basis for a system of advanced
programmable interrupt controllers (APICs) originally designed by Intel but
now widely used on all x86 systems.
There are two elements in the architecture, the local APIC (LAPIC) and the I/O
APIC. Historically these were connected by a dedicated 3-wire “APIC
bus”, but the system bus is used for communication today. The
configuration is increasingly dependent on ACPI.
Typically each CPU in the system contains one LAPIC that performs two primary
functions:
- It receives interrupts both from internal sources and from
the external I/O APIC. The interrupt sources include I/O devices, the
programmable APIC timer, performance monitoring counters, thermal sensor
interrupts, and others.
- In multiprocessor (MP) systems a LAPIC receives and sends
interprocessor interrupts (IPIs) from and to other processors in the
system. IPIs are used to provide software interrupts, interrupt
forwarding, or preemptive scheduling. Against this, the architecture can
be generally seen as an attempt to solve the interrupt routing efficiency
issues in MP systems.
There is typically one I/O APIC for each peripheral bus in the system. Each I/O
APIC has a series of interrupt inputs to external interrupt sources. The
architecture usually contains a redirection table which can be used to route
the interrupts that an I/O APIC receives to one or more local APICs. When a
LAPIC is able to accept an interrupt, it will signal the CPU. Without an I/O
APIC, the local APICs are therefore mostly useless; one of the primary
functions of the architecture is no longer achievable, interrupts can not be
distributed to different CPUs.
The 8259 PIC has coexisted with the architecture since its introduction. It is
still possible to disable the APIC system and revert back to a 8259-compatible
PIC. But the widespread use of MP systems has made this mainly a fallback
option.
SEE ALSO
acpi(4),
mainbus(4),
x86/ichlpcib(4)
Intel Corporation,
Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A: System Programming Guide, Part
1,
http://www.intel.com/Assets/PDF/manual/253668.pdf,
Chapter 10, January,
2011.
Intel Corporation,
Intel 82093AA I/O Advanced Programmable,
Interrupt Controller (I/O APIC) Datasheet,
http://www.intel.com/design/chipsets/datashts/29056601.pdf,
May, 1996.
Intel Corporation,
8259A, Programmable Interrupt Controller,
http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf,
December, 1988.
John Baldwin, PCI
Interrupts for x86 Machines under FreeBSD,
http://people.freebsd.org/~jhb/papers/bsdcan/2007/article.pdf,
May 18-19, 2007, Proceedings of
BSDCan 2007.
Microsoft Corporation,
PCI IRQ Routing on a Multiprocessor ACPI System,
http://www.microsoft.com/whdc/archive/acpi-mp.mspx,
December 4, 2001.
AUTHORS
Authors of the
NetBSD implementation of the Intel APIC
Architecture include
Andrew Doran,
Bill Sommerfeld,
Frank van der
Linden, and
Stefan Grefen, among others. The
older 8259 PIC implementation is based on the work of
William
Jolitz.