NAME
epgpio —
General Purpose I/O support
for Cirrus EP93xx ARM processors
SYNOPSIS
epgpio0 at epsoc? addr 0x80840000 size 0xcc intr 59
gpio* at epgpio?
options EPGPIO_PORT_A_MASK=0xXX
options EPGPIO_PORT_B_MASK=0xXX
options EPGPIO_PORT_C_MASK=0xXX
options EPGPIO_PORT_D_MASK=0xXX
options EPGPIO_PORT_E_MASK=0xXX
options EPGPIO_PORT_F_MASK=0xXX
options EPGPIO_PORT_G_MASK=0xXX
options EPGPIO_PORT_H_MASK=0xXX
DESCRIPTION
The
epgpio driver provides support for the on-board General
Purpose I/O (GPIO) pins on the Cirrus Logic EP93xx series of processors. There
are 8 GPIO ports (Ports A though H) each having 8 GPIO pins available (note:
early revisions of some EP9301 processors have some ports with less than eight
pins available on each port; check the documentation for your specific
processor).
The
epgpio driver provides a
gpio(4) controller interface
and will attach each port as a separate
gpio(4) device with 8 pins
available. All pins are bidirectional; when used as inputs they should not be
driven beyond TTL voltage levels, but for exact details on the electrical
interface the documentation for the specific evbarm board should be consulted.
Kernel options
The following kernel options are available to configure the behavior of the
epgpio driver.
- options
EPGPIO_PORT_A_MASK=0xXX
-
- options
EPGPIO_PORT_B_MASK=0xXX
-
- options
EPGPIO_PORT_C_MASK=0xXX
-
- options
EPGPIO_PORT_D_MASK=0xXX
-
- options
EPGPIO_PORT_E_MASK=0xXX
-
- options
EPGPIO_PORT_F_MASK=0xXX
-
- options
EPGPIO_PORT_G_MASK=0xXX
-
- options
EPGPIO_PORT_H_MASK=0xXX
-
Each of these options is a bitmask specifying the pins available to the
gpio(4) controller for the
corresponding port. Pins should be disabled if they are not available or are
being used by the hardware for other purposes. The default mask is
“0xff” for all ports.
IMPLEMENTATION NOTES
When a port bitmask configures less than 8 pins available, the remaining pins
will appear as sequentially numbered pins to the
gpio(4) interface. For example,
if
EPGPIO_PORT_A_MASK
is set to “0x2c”,
Port A pins 1, 3, and 5 will appear as
gpio(4) pins 0, 1, and 2
respectively.
SEE ALSO
gpio(4)